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v4.3
eX Family FPGAs
FuseLock
Leading Edge Performance
* * * 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out (Pad-to-Pad)
* * * * * *
Specifications
* * * * 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros) 0.22m CMOS Process Technology Up to 132 User-Programmable I/O Pins
* * * * *
Features
* * * * * * High-Performance, Low-Power Antifuse FPGA LP/Sleep Mode for Additional Power Savings Advanced Small-Footprint Packages Hot-Swap Compliant I/Os Single-Chip Solution Nonvolatile
Live on Power-Up No Power-Up/Down Sequence Required for Supply Voltages Configurable Weak-Resistor Pull-Up or Pull-Down for Tristated Outputs during Power-Up Individual Output Slew Rate Control 2.5 V, 3.3 V, and 5.0 V Mixed-Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength Software Design Support with Actel Designer and LiberoTM Integrated Design Environment (IDE) Tools Up to 100% Resource Utilization with 100% Pin Locking Deterministic Timing Unique In-System Diagnostic and Verification Capability with Silicon Explorer II Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) FuselockTM Secure Programming Technology Prevents Reverse Engineering and Design Theft
Product Profile
Device Capacity System Gates Typical Gates Register Cells Dedicated Flip-Flops Maximum Flip-Flops Combinatorial Cells Maximum User I/Os Global Clocks Hardwired Routed Speed Grades Temperature Grades* Package (by pin count) TQFP CSP eX64 3,000 2,000 64 128 128 84 1 2 -F, Std, -P C, I, A 64, 100 49, 128 eX128 6,000 4,000 128 256 256 100 1 2 -F, Std, -P C, I, A 64, 100 49, 128 eX256 12,000 8,000 256 512 512 132 1 2 -F, Std, -P C, I, A 100 128, 180
Note: *Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings.
June 2006 (c) 2006 Actel Corporation
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eX Family FPGAs
Ordering Information
eX128 P TQ G 100 Application (Ambient Temperature Range) Blank = I= A= PP = Commercial (0C to 70C) Industrial (-40C to 85C) Automotive (-40C to 125C) Pre-production
Package Lead Count
Lead-Free Packaging Blank = Standard Packaging G = RoHS Compliant Packaging
Package Type TQ = Thin Quad Flat Pack (0.5 mm pitch) CS = Chip-Scale Package (0.8 mm pitch) Speed Grade Blank= Standard Speed P = Approximately 30% Faster than Standard F = Approximately 40% Slower than Standard Part Number eX64 = 64 Dedicated Flip-Flops (3,000 System Gates) eX128 = 128 Dedicated Flip-Flops (6,000 System Gates) eX256 = 256 Dedicated Flip-Flops (12,000 System Gates)
Plastic Device Resources
Device eX64 eX128 eX256 TQFP 64-Pin 41 46 -- User I/Os (Including Clock Buffers) TQFP 100-Pin CSP 49-Pin CSP 128-Pin 56 36 84 70 36 100 81 -- 100 CSP 180-Pin -- -- 132
Note: Package Definitions:TQFP = Thin Quad Flat Pack, CSP = Chip Scale Package
Temperature Grade Offerings
Device\Package eX64 eX128 eX256 Notes: C = Commercial I = Industrial A = Automotive TQFP 64-Pin C, I, A C, I, A C, I, A TQFP 100-Pin C, I, A C, I, A C, I, A CSP 49-Pin C, I, A C, I, A C, I, A CSP 128-Pin C, I, A C, I, A C, I, A CSP 180-Pin C, I, A C, I, A C, I, A
Speed Grade and Temperature Grade Matrix
C I A Notes: P = Approximately 30% faster than Standard -F = Approximately 40% slower than Standard Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings. -F Std -P
Contact your local Actel representative for device availability.
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v4.3
eX Family FPGAs
Table of Contents
eX Family FPGAs
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 eX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 2.5V/3.3V/5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 2.5V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 5.0V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 eX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 eX Family Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Package Pin Assignments
64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 49-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 128-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 180-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
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eX Family FPGAs
eX Family FPGAs
General Description
The eX family of FPGAs is a low-cost solution for lowpower, high-performance designs. The inherent low power attributes of the antifuse technology, coupled with an additional low static power mode, make these devices ideal for power-sensitive applications. Fabricated with an advanced 0.22m CMOS antifuse technology, these devices achieve high performance with no power penalty. impedance connection. Actel's eX family provides two types of logic modules, the register cell (R-cell) and the combinatorial cell (C-cell). The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals (Figure 1-1). The R-cell registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional flexibility while allowing mapping of synthesized functions into the eX FPGA. The clock source for the Rcell can be chosen from either the hard-wired clock or the routed clock. The C-cell implements a range of combinatorial functions up to five inputs (Figure 1-2 on page 1-2). Inclusion of the DB input and its associated inverter function enables the implementation of more than 4,000 combinatorial functions in the eX architecture in a single module. Two C-cells can be combined together to create a flipflop to imitate an R-cell via the use of the CC macro. This is particularly useful when implementing non-timingcritical paths and when the design engineer is running out of R-cells. More information about the CC macro can be found in Actel's Maximizing Logic Utilization in eX, SX and SX-A FPGA Devices Using CC Macros application note.
eX Family Architecture
Actel's eX family is implemented on a high-voltage twinwell CMOS process using 0.22m design rules. The eX family architecture uses a "sea-of-modules" structure where the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. Interconnection among these logic modules is achieved using Actel's patented metal-to-metal programmable antifuse interconnect elements. The antifuse interconnect is made up of a combination of amorphous silicon and dielectric material with barrier metals and has an "on" state resistance of 25 with a capacitance of 1.0fF for low-signal impedance. The antifuses are normally open circuit and, when programmed, form a permanent low-
S0
Routed Data Input S1 PSET
DirectConnect Input
D
Q
Y
HCLK CLKA, CLKB, Internal Logic CKS
Figure 1-1 * R-Cell
CLR
CKP
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eX Family FPGAs
Module Organization
C-cell and R-cell logic modules are arranged into horizontal banks called Clusters, each of which contains two C-cells and one R-cell in a C-R-C configuration. Clusters are further organized into modules called SuperClusters for improved design efficiency and device performance, as shown in Figure 1-3. Each SuperCluster is a two-wide grouping of Clusters.
D0 D1 Y D2 D3 Sa Sb
DB A0 B0
Figure 1-2 * C-Cell
R-Cell
Routed Data Input S1 PSET DirectConnect Input D2 D Q Y D3 Sa HCLK CLKA, CLKB, Internal Logic Sb D0 D1 Y
A1 B1
C-Cell
S0
CLR DB CKS CKP A0 B0 A1 B1
Cluster SuperCluster
Cluster
Figure 1-3 * Cluster Organization
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eX Family FPGAs
Routing Resources
Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within Clusters and SuperClusters (Figure 1-4). This routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance. DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring Rcell in a given SuperCluster. DirectConnect uses a hardwired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns (-P speed grade). FastConnect enables horizontal routing between any two logic modules within a given SuperCluster and vertical routing with the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering maximum pin-to-pin propagation of 0.3 ns (-P speed grade). In addition to DirectConnect and FastConnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. Actel's segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the fully automatic place-and-route software to minimize signal propagation delays.
SuperClusters
DirectConnect * No antifuses * 0.1 ns routing delay
FastConnect * One antifuse * 0.5 ns routing delay
Routing Segments * Typically 2 antifuses * Max. 5 antifuses
Figure 1-4 * DirectConnect and FastConnect for SuperClusters
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eX Family FPGAs
Clock Resources
eX's high-drive routing structure provides three clock networks. The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in each R-Cell. HCLK cannot be connected to combinational logic. This provides a fast propagation path for the clock signal, enabling the 3.9 ns clock-to-out (pad-to-pad) performance of the eX devices. The hard-wired clock is tuned to provide a clock skew of less than 0.1 ns worst case. If not used, the HCLK pin must be tied LOW or HIGH and must not be left floating. Figure 1-5 describes the clock circuit used for the constant load HCLK. HCLK does not function until the fourth clock cycle each time the device is powered up to prevent false output levels due to any possible slow power-on-reset signal and fast start-up clock circuit. To activate HCLK from the first cycle, the TRST pin must be reserved in the Design software and the pin must be tied to GND on the board. (See the "TRST, I/O Boundary Scan Reset Pin" on page 126).
The remaining two clocks (CLKA, CLKB) are global routed clock networks that can be sourced from external pins or from internal logic signals (via the CLKINT routed clock buffer) within the eX device. CLKA and CLKB may be connected to sequential cells or to combinational logic. If CLKA or CLKB is sourced from internal logic signals, the external clock pin cannot be used for any other input and must be tied LOW or HIGH and must not float. Figure 1-6 describes the CLKA and CLKB circuit used in eX devices. Table 1-1 describes the possible connections of the routed clock networks, CLKA and CLKB. Unused clock pins must not be left floating and must be tied to HIGH or LOW.
Constant Load Clock Network HCLKBUF
Figure 1-5 * eX HCLK Clock Pad
Clock Network
From Internal Logic CLKBUF CLKBUFI CLKINT CLKINTI
Figure 1-6 * eX Routed Clock Buffer Table 1-1 * Connections of Routed Clock Networks, CLKA and CLKB Module C-Cell R-Cell I/O-Cell Pins A0, A1, B0 and B1 CLKA, CLKB, S0, S1, PSET, and CLR EN
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eX Family FPGAs
Other Architectural Features
Performance
The combination of architectural features described above enables eX devices to operate with internal clock frequencies exceeding 350 MHz for very fast execution of complex logic functions. The eX family is an optimal platform upon which the functionality previously contained in CPLDs can be integrated. eX devices meet the performance goals of gate arrays, and at the same time, present significant improvements in cost and time to market. Using timing-driven place-and-route tools, designers can achieve highly deterministic device performance. All unused I/Os are configured as tristate outputs by Actel's Designer software, for maximum flexibility when designing new boards or migrating existing designs. Each I/O module has an available pull-up or pull-down resistor of approximately 50 k that can configure the I/O in a known state during power-up. Just shortly before VCCA reaches 2.5 V, the resistors are disabled and the I/Os will be controlled by user logic. Table 1-2 describes the I/O features of eX devices. For more information on I/Os, refer to Actel eX, SX-A, and RT54SX-S I/Os application note.
Table 1-2 * I/O Features Function Description 5.0V TTL 3.3V LVTTL 2.5V LVCMOS2 5.0V TTL/CMOS 3.3V LVTTL 2.5V LVCMOS 2 I/O on an unpowered device does not sink current Can be used for "cold sparing" Input Buffer * Threshold * Selection * Nominal Output Drive * * * * *
User Security
The Actel FuseLock advantage ensures that unauthorized users will not be able to read back the contents of an Actel antifuse FPGA. In addition to the inherent strengths of the architecture, special security fuses that prevent internal probing and overwriting are hidden throughout the fabric of the device. They are located such that they cannot be accessed or bypassed without destroying the rest of the device, making both invasive and more-subtle noninvasive attacks ineffective against Actel antifuse FPGAs. Look for this symbol to ensure your valuable IP is secure.
Output Buffer "Hot-Swap" Capability
Selectable on an individual I/O basis Individually selectable low-slew option Power-Up Individually selectable pull ups and pull downs during power-up (default is to power up in tristate) Enables deterministic power-up of device VCCA and VCCI can be powered in any order
FuseLock
Figure 1-7 * Fuselock
For more information, refer to Actel's Implementation of Security in Actel Antifuse FPGAs application note.
The eX family supports mixed-voltage operation and is designed to tolerate 5.0 V inputs in each case. A detailed description of the I/O pins in eX devices can be found in "Pin Description" on page 1-26.
I/O Modules
Each I/O on an eX device can be configured as an input, an output, a tristate output, or a bidirectional pin. Even without the inclusion of dedicated I/O registers, these I/ Os, in combination with array registers, can achieve clock-to-out (pad-to-pad) timing as fast as 3.9 ns. I/O cells in eX devices do not contain embedded latches or flipflops and can be inferred directly from HDL code. The device can easily interface with any other device in the system, which in turn enables parallel design of system components and reduces overall design time.
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eX Family FPGAs
Hot Swapping
eX I/Os are configured to be hot-swappable. During power-up/down (or partial up/down), all I/Os are tristated, provided VCCA ramps up within a diode drop of VCCI. VCCA and VCCI do not have to be stable during power-up/down, and they do not require a specific power-up or power-down sequence in order to avoid damage to the eX devices. In addition, all outputs can be programmed to have a weak resistor pull-up or pulldown for output tristate at power-up. After the eX device is plugged into an electrically active system, the device will not degrade the reliability of or cause damage to the host system. The device's output pins are driven to a high impedance state until normal chip operating conditions are reached. Please see the application note, Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications, which also applies to the eX devices, for more information on hot swapping.
Low Power Mode
The eX family has been designed with a Low Power Mode. This feature, activated with setting the special LP pin to HIGH for a period longer than 800 ns, is particularly useful for battery-operated systems where battery life is a primary concern. In this mode, the core of the device is turned off and the device consumes minimal power with low standby current. In addition, all input buffers are turned off, and all outputs and bidirectional buffers are tristated when the device enters this mode. Since the core of the device is turned off, the states of the registers are lost. The device must be re-initialized when returning to normal operating mode. I/Os can be driven during LP mode. For details, refer to the Design for Low Power in Actel Antifuse FPGAs application note under the section Using the LP Mode Pin on eX Devices. Clock pins should be driven either HIGH or LOW and should not float; otherwise, they will draw current and burn power. The device must be re-initialized when exiting LP mode. To exit the LP mode, the LP pin must be driven LOW for over 200s to allow for the charge pumps to power-up and device initialization can begin. Table 1-3 illustrates the standby current of eX devices in LP mode.
Table 1-3 * Standby Power of eX Devices in LP Mode Typical Conditions, VCCA, VCCI = 2.5 V, TJ = 25 C Product eX64 eX128 eX256 Low Power Standby Current 100 111 134 Units A A A
Power Requirements
Power consumption is extremely low for the eX family due to the low capacitance of the antifuse interconnects. The antifuse architecture does not require active circuitry to hold a charge (as do SRAM or EPROM), making it the lowest-power FPGA architecture available today.
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eX Family FPGAs
Figure 1-8 to Figure 1-11 on page 1-8 show some sample power characteristics of eX devices.
300 250 Power (mW) 200 150 100 50 0 50 100 150 200 Frequency (MHz) eX64 eX128 eX256
Notes: 1. Device filled with 16-bit counters. 2. VCCA, VCCI = 2.7 V, device tested at room temperature. Figure 1-8 * eX Dynamic Power Consumption - High Frequency
80 70 60 Power (mW) 50 40 30 20 10 0 0 10 20 30 40 50 Frequency (MHz) eX64 eX128 eX256
Notes: 1. Device filled with 16-bit counters. 2. VCCA, VCCI = 2.7 V, device tested at room temperature. Figure 1-9 * eX Dynamic Power Consumption - Low Frequency
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eX Family FPGAs
180 160
Total Dynamic Power (mW)
140 120 100 80 60 40 20 0 0 25 50 75 100 125 150 175 200 32-bit Decoder 8 x 8-bit Counters SDRAM Controller
Frequency (MHz)
Figure 1-10 * Total Dynamic Power (mW)
12,000 10,000
System Power (uW)
8,000 5% DC 6,000 4,000 2,000 0 0 10 20 30 40 50 60 10% DC 15% DC
Frequency (MHz)
Figure 1-11 * System Power at 5%, 10%, and 15% Duty Cycle
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eX Family FPGAs
Boundary Scan Testing (BST)
All eX devices are IEEE 1149.1 compliant. eX devices offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. These functions are controlled through the special test pins (TMS, TDI, TCK, TDO and TRST). The functionality of each pin is defined by two available modes: Dedicated and Flexible, and is described in Table 1-4. In the dedicated test mode, TCK, TDI, and TDO are dedicated pins and cannot be used as regular I/Os. In flexible mode (default mode), TMS should be set HIGH through a pullup resistor of 10 k. TMS can be pulled LOW to initiate the test sequence.
Table 1-4 * Boundary Scan Pin Functionality Dedicated Test Mode Flexible Mode
Flexible Mode
In Flexible Mode, TDI, TCK and TDO may be used as either user I/Os or as JTAG input pins. The internal resistors on the TMS and TDI pins are disabled in flexible JTAG mode, and an external 10 k pull-resistor to VCCI is required on the TMS pin. To select the Flexible mode, users need to uncheck the "Reserve JTAG" box in "Device Selection Wizard" in Actel's Designer software. The functionality of TDI, TCK, and TDO pins is controlled by the BST TAP controller. The TAP controller receives two control inputs, TMS and TCK. Upon power-up, the TAP controller enters the Test-LogicReset state. In this state, TDI, TCK, and TDO function as user I/Os. The TDI, TCK, and TDO pins are transformed from user I/Os into BST pins when the TMS pin is LOW at the first rising edge of TCK. The TDI, TCK, and TDO pins return to user I/Os when TMS is held HIGH for at least five TCK cycles. Table 1-5 describes the different configuration requirements of BST pins and their functionality in different modes.
Table 1-5 * Boundary-Scan Pin Configurations and Functions Designer "Reserve JTAG" Selection Checked Unchecked Unchecked TAP Controller State Any Test-Logic-Reset Any EXCEPT TestLogic-Reset
TCK, TDI, TDO are dedicated TCK, TDI, TDO are flexible and BST pins may be used as I/Os No need for pull-up resistor for Use a pull-up resistor of 10 k TMS and TDI on TMS
Dedicated Test Mode
In Dedicated mode, all JTAG pins are reserved for BST; designers cannot use them as regular I/Os. An internal pull-up resistor is automatically enabled on both TMS and TDI pins, and the TMS pin will function as defined in the IEEE 1149.1 (JTAG) specification. To select Dedicated mode, users need to reserve the JTAG pins in Actel's Designer software by checking the "Reserve JTAG" box in "Device Selection Wizard" (Figure 1-12). JTAG pins comply with LVTTL/TTL I/O specification regardless of whether they are used as a user I/O or a JTAG I/O. Refer to the "3.3V LVTTL Electrical Specifications" and "5.0V TTL Electrical Specifications" on page 1-15 for detailed specifications.
Mode Dedicated (JTAG) Flexible (User I/O) Flexible (JTAG)
TRST Pin
The TRST pin functions as a dedicated Boundary-Scan Reset pin when the "Reserve JTAG Test Reset" option is selected as shown in Figure 1-12. An internal pull-up resistor is permanently enabled on the TRST pin in this mode. It is recommended to connect this pin to GND in normal operation to keep the JTAG state controller in the Test-Logic-Reset state. When JTAG is being used, it can be left floating or be driven HIGH. When the "Reserve JTAG Test Reset" option is not selected, this pin will function as a regular I/O. If unused as an I/O in the design, it will be configured as a tristated output.
Figure 1-12 * Device Selection Wizard
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eX Family FPGAs
JTAG Instructions
Table 1-6 lists the supported instructions with the corresponding IR codes for eX devices.
Table 1-6 * JTAG Instruction Code Instructions (IR4: IR0) EXTEST SAMPLE / PRELOAD INTEST USERCODE IDCODE HIGHZ CLAMP Diagnostic BYPASS Reserved Binary Code 00000 00001 00010 00011 00100 01110 01111 10000 11111 All others
1. Load the .AFM file 2. Select the device to be programmed 3. Begin programming When the design is ready to go to production, Actel offers device volume-programming services either through distribution partners or via in-house programming from the factory. For more details on programming eX devices, please refer to the Programming Antifuse Devices application note and the Silicon Sculptor II User's Guide.
Probing Capabilities
eX devices provide internal probing capability that is accessed with the JTAG pins. The Silicon Explorer II Diagnostic hardware is used to control the TDI, TCK, TMS and TDO pins to select the desired nets for debugging. The user simply assigns the selected internal nets in the Silicon Explorer II software to the PRA/PRB output pins for observation. Probing functionality is activated when the BST pins are in JTAG mode and the TRST pin is driven HIGH or left floating. If the TRST pin is held LOW, the TAP controller will remain in the Test-Logic-Reset state so no probing can be performed. The Silicon Explorer II automatically places the device into JTAG mode, but the user must drive the TRST pin HIGH or allow the internal pull-up resistor to pull TRST HIGH. When you select the "Reserve Probe Pin" box as shown in Figure 1-12 on page 1-9, the layout tool reserves the PRA and PRB pins as dedicated outputs for probing. This "reserve" option is merely a guideline. If the Layout tool requires that the PRA and PRB pins be user I/Os to achieve successful layout, the tool will use these pins for user I/Os. If you assign user I/Os to the PRA and PRB pins and select the "Reserve Probe Pin" option, Designer Layout will override the "Reserve Probe Pin" option and place your user I/Os on those pins. To allow for probing capabilities, the security fuse must not be programmed. Programming the security fuse will disable the probe circuitry. Table 1-8 on page 1-11 summarizes the possible device configurations for probing once the device leaves the "Test-Logic-Reset" JTAG state.
Table 1-7 lists the codes returned after executing the IDCODE instruction for eX devices. Note that bit 0 is always "1." Bits 11-1 are always "02F", which is Actel's manufacturer code.
Table 1-7 * IDCODE for eX Devices Device eX64 eX128 eX256 eX64 eX128 eX256 Revision 0 0 0 1 1 1 Bits 31-28 8 9 9 A B B Bits 27-12 40B2, 42B2 40B0, 42B0 40B5, 42B5 40B2, 42B2 40B0, 42B0 40B5, 42B5
Programming
Device programming is supported through Silicon Sculptor series of programmers. In particular, Silicon Sculptor II is a compact, robust, single-site and multi-site device programmer for the PC. With standalone software, Silicon Sculptor II allows concurrent programming of multiple units from the same PC, ensuring the fastest programming times possible. Each fuse is subsequently verified by Silicon Sculptor II to insure correct programming. In addition, integrity tests ensure that no extra fuses are programmed. Silicon Sculptor II also provides extensive hardware self-testing capability. The procedure for programming an eX device using Silicon Sculptor II is as follows:
Silicon Explorer II Probe
Silicon Explorer II is an integrated hardware and software solution that, in conjunction with Actel's Designer software tools, allow users to examine any of the internal nets of the device while it is operating in a prototype or a production system. The user can probe into an eX device via the PRA and PRB pins without changing the placement and routing of the design and without using any additional resources. Silicon
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Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle. Silicon Explorer II does not require re-layout or additional MUXes to bring signals out to an external pin, which is necessary when using programmable logic devices from other suppliers. Silicon Explorer II samples data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds. The Silicon Explorer II tool uses the boundary scan ports (TDI, TCK, TMS and TDO) to select the desired nets for verification. The selected internal nets are assigned to the PRA/PRB pins for observation. Figure 1-13 illustrates the
TRST1 LOW LOW HIGH HIGH -
interconnection between Silicon Explorer II and the eX device to perform in-circuit verification.
Design Considerations
The TDI, TCK, TDO, PRA, and PRB pins should not be used as input or bidirectional ports. Since these pins are active during probing, critical signals input through these pins are not available while probing. In addition, the Security Fuse should not be programmed because doing so disables the probe circuitry. It is recommended to use a series 70 termination resistor on every probe connector (TDI, TCK, TMS, TDO, PRA, PRB). The 70 series termination is used to prevent data transmission corruption during probing and reading back the checksum.
Table 1-8 * Device Configuration Options for Probe Capability (TRST pin reserved) JTAG Mode Dedicated Flexible Dedicated Flexible - Notes: 1. If TRST pin is not reserved, the device behaves according to TRST = HIGH in the table. 2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input signals will not pass through these pins and may cause contention. 3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by Actel's Designer software. Security Fuse Programmed No No No No Yes PRA, PRB2 User I/O3 User I/O
3
TDI, TCK, TDO2 Probing Unavailable User I/O3 Probe Circuit Inputs Probe Circuit Inputs Probe Circuit Secured
Probe Circuit Outputs Probe Circuit Outputs Probe Circuit Secured
16 Pin Connection Serial Connection Silicon Explorer II TDI TCK TMS TDO PRA PRB 22 Pin Connection Additional 16 Channels (Logic Analyzer)
Figure 1-13 * Silicon Explorer II Probe Setup
eX FPGAs
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eX Family FPGAs
Development Tool Support
The eX family of FPGAs is fully supported by both Actel's LiberoTM Integrated Design Environment and Designer FPGA Development software. Actel Libero IDE is a design management environment that streamlines the design flow. Libero IDE provides an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes Synplify(R) for Actel from Synplicity(R), ViewDraw for Actel from Mentor Graphics, ModelSimTM HDL Simulator from Mentor Graphics(R), WaveFormer LiteTM from SynaptiCADTM, and Designer software from Actel. Refer to the Libero IDE flow (located on Actel's website) diagram for more information. Actel's Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes timing-driven place-and-route, and a world-class integrated static timing analyzer and constraints editor. With the Designer software, a user can lock his/her design pins before layout while minimally impacting the results of place-and-route. Additionally, the backannotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Actel's integrated verification and logic analysis tool. Another tool included in the Designer software is the SmartGen core generator, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems.
Related Documents
Datasheet
eX Automotive Family FPGAs http://www.actel.com/documents/eXAuto_DS.pdf
Application Notes
Maximizing Logic Utilization in eX, SX and SX-A FPGA Devices Using CC Macros http://www.actel.com/documents/CC_Macro_AN.pdf Actel's Implementation of Security in Actel Antifuse FPGAs http://www.actel.com/documents/ Antifuse_Security_AN.pdf Actel eX, SX-A, and RT54SX-S I/Os http://www.actel.com/documents/antifuseIO_AN.pdf Actel SX-A and RT54SX-S Devices in Hot-Swap and ColdSparing Applications http://www.actel.com/documents/ HotSwapColdSparing_AN.pdf Design For Low Power in Actel Antifuse FPGAs http://www.actel.com/documents/Low_Power_AN.pdf Programming Antifuse Devices http://www.actel.com/documents/ AntifuseProgram_AN.pdf
User Guides
Silicon Sculptor II User's Guide http://www.actel.com/techdocs/manuals/ default.asp#programmers
Miscellaneous
Libero IDE flow http://www.actel.com/products/tools/libero/flow.html
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2.5 V / 3.3 V /5.0 V Operating Conditions
Table 1-9 * Absolute Maximum Ratings* Symbol VCCI VCCA VI VO TSTG Parameter DC Supply Voltage for I/Os DC Supply Voltage for Array Input Voltage Output Voltage Storage Temperature Limits -0.3 to +6.0 -0.3 to +3.0 -0.5 to +5.75 -0.5 to +VCCI -65 to +150 Units V V V V C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 1-10 * Recommended Operating Conditions Parameter Temperature Range* 2.5V Power Supply Range (VCCA, VCCI) 3.3V Power Supply Range (VCCI) 5.0V Power Supply Range (VCCI) Note: *Ambient temperature (TA). Table 1-11 * Typical eX Standby Current at 25C Product eX64 eX128 eX256 VCCA= 2.5 V VCCI = 2.5 V 397 A 696 A 698 A VCCA = 2.5 V VCCI = 3.3 V 49 7A 795 A 796 A VCCA = 2.5 V VCCI = 5.0 V 700 A 1,000 A 2,000 A Commercial 0 to +70 2.3 to 2.7 3.0 to 3.6 4.75 to 5.25 Industrial -40 to +85 2.3 to 2.7 3.0 to 3.6 4.75 to 5.25 Units C V V V
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2.5 V LVCMOS2 Electrical Specifications
Commercial Symbol VOH Parameter VCCI = MIN, VI = VIH or VIL VCCI = MIN, VI = VIH or VIL VCCI = MIN, VI = VIH or VIL VOL VCCI = MIN, VI = VIH or VIL VCCI = MIN, VI = VIH or VIL VCCI = MIN,VI = VIH or VIL VIL VIH IIL/ IIH IOZ tR, tF CIO ICC3,4 IV Curve Notes: 1. 2. 3. 4. tR is the transition time from 0.7 V to 1.7 V. tF is the transition time from 1.7 V to 0.7 V. ICC max Commercial -F = 5.0 mA ICC = ICCI + ICCA
1,2
Industrial Min. 2.1 2.0 1.7 Max. Units V V V 0.2 0.4 0.7 -0.3 1.7 -10 -10 0.7 VCCI + 0.3 10 10 10 10 3.0 V V V V V A A ns pF mA
Min. (IOH = -100 A) (IOH = -1 mA) (IOH = -2 mA) (IOL= 100 A) (IOL= 1mA) (IOL= 2 mA) -0.3 1.7 -10 -10 2.1 2.0 1.7
Max.
0.2 0.4 0.7 0.7 VCCI + 0.3 10 10 10 10 1.0
Input Low Voltage, VOUT VOL(max) Input High Voltage, VOUT VOH(min) Input Leakage Current, VIN = VCCI or GND 3-State Output Leakage Current, VOUT = VCCI or GND Input Transition Time I/O Capacitance Standby Current
Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.
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3.3 V LVTTL Electrical Specifications
Commercial Symbol VOH VOL VIL VIH IIL/ IIH IOZ tR, tF1,2 CIO ICC3,4 IV Curve Notes: 1. 2. 3. 4. 5. tR is the transition time from 0.8 V to 2.0 V. tF is the transition time from 2.0 V to 0.8 V. ICC max Commercial -F = 5.0 mA ICC = ICCI + ICCA JTAG pins comply with LVTTL/TTL I/O specification regardless of whether they are used as a user I/O or a JTAG I/O. Parameter VCCI = MIN, VI = VIH or VIL VCCI = MIN, VI = VIH or VIL Input Low Voltage Input High Voltage Input Leakage Current, VIN = VCCI or GND 3-State Output Leakage Current, VOUT = VCCI or GND Input Transition Time I/O Capacitance Standby Current Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html. 2.0 -10 -10 (IOH = -8 mA) (IOL= 12 mA) Min. 2.4 0.4 0.8 VCCI +0.5 10 10 10 10 1.5 2.0 -10 -10 Max. Industrial Min. 2.4 0.4 0.8 VCCI +0.5 10 10 10 10 10 Max. Units V V V V A A ns pF mA
5.0 V TTL Electrical Specifications
Commercial Symbol VOH VOL VIL VIH IIL/ IIH IOZ tR, tF1,2 CIO ICC3,4 IV Curve Note: 1. 2. 3. 4. 5. tR is the transition time from 0.8 V to 2.0 V. tF is the transition time from 2.0 V to 0.8 V. ICC max Commercial -F=20mA ICC = ICCI + ICCA JTAG pins comply with LVTTL/TTL I/O specification regardless of whether they are used as a user I/O or a JTAG I/O. Parameter VCCI = MIN, VI = VIH or VIL VCCI = MIN, VI = VIH or VIL Input Low Voltage Input High Voltage Input Leakage Current, VIN = VCCI or GND 3-State Output Leakage Current, VOUT = VCCI or GND Input Transition Time I/O Capacitance Standby Current Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html. 2.0 -10 -10 (IOH = -8 mA) (IOL= 12 mA) Min. 2.4 0.4 0.8 VCCI +0.5 10 10 10 10 15 2.0 -10 -10 Max. Industrial Min. 2.4 0.4 0.8 VCCI +0.5 10 10 10 10 20 Max. Units V V V V A A ns pF mA
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eX Family FPGAs
Power Dissipation
Power consumption for eX devices can be divided into two components: static and dynamic.
CEQ Values for eX Devices
Combinatorial modules (Ceqcm) Sequential modules (Ceqsm) Input buffers (Ceqi) Output buffers (Ceqo) Routed array clocks (Ceqcr) 1.70 pF 1.70 pF 1.30 pF 7.40 pF 1.05 pF
Static Power Component
The power due to standby current is typically a small component of the overall power. Typical standby current for eX devices is listed in the Table 1-11 on page 1-13. For example, the typical static power for eX128 at 3.3 V VCCI is: ICC * VCCA = 795 A x 2.5 V = 1.99 mW
The variable and fixed capacitance of other device components must also be taken into account when estimating the dynamic power dissipation. Table 1-12 shows the capacitance components of eX devices. of the clock
Dynamic Power Component
Power dissipation in CMOS devices is usually dominated by the dynamic power dissipation. This component is frequency-dependent and a function of the logic and the external I/O. Dynamic power dissipation results from charging internal chip capacitance due to PC board traces and load device inputs. An additional component of the dynamic power dissipation is the totem pole current in the CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent dynamic power dissipation. Dynamic power dissipation = CEQ * VCCA x F where: CEQ = Equivalent capacitance F = switching frequency Equivalent capacitance is calculated by measuring ICCA at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown below.
2
Table 1-12 * Capacitance of Clock Components of eX Devices eX64 Dedicated array variable (Ceqhv) clock - 0.85 pF eX128 0.85 pF 20.00 pF 28.00 pF 28.00 pF eX256 0.85 pF 25.00 pF 35.00 pF 35.00 pF
Dedicated array clock - fixed 18.00 pF (Ceqhf) Routed array clock A (r1) Routed array clock B (r2) 23.00 pF 23.00 pF
The estimation of the dynamic power dissipation is a piece-wise linear summation of the power dissipation of each component. Dynamic power dissipation = VCCA2 * [(mc * Ceqcm * fmC)Comb Modules + (ms * Ceqsm * fmS)Seq Modules + (n * Ceqi * fn)Input Buffers + (0.5 * (q1 * Ceqcr * fq1) + (r1 * fq1))RCLKA + (0.5 * (q2 * Ceqcr * fq2) + (r2 * fq2))RCLKB + (0.5 * (s1 * Ceqhv * fs1)+(Ceqhf * fs1))HCLK] + VCCI2 * [(p * (Ceqo + CL) * fp)Output Buffers] where: mc = Number of combinatorial cells switching at frequency fm, typically 20% of C-cells = Number of sequential cells switching at ms frequency fm, typically 20% of R-cells n = Number of input buffers switching at frequency fn, typically number of inputs / 4 p = Number of output buffers switching at frequency fp, typically number of outputs / 4 q1 = Number of R-cells driven by routed array clock A q2 = Number of R-cells driven by routed array clock B r1 = Fixed capacitance due to routed array clock A r2 = Fixed capacitance due to routed array clock B s1 = Number of R-cells driven by dedicated array clock Ceqcm = Equivalent capacitance of combinatorial modules
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Equivalent capacitance of sequential modules Ceqi = Equivalent capacitance of input buffers Ceqcr = Equivalent capacitance of routed array clocks Ceqhv = Variable capacitance of dedicated array clock Ceqhf = Fixed capacitance of dedicated array clock Ceqo = Equivalent capacitance of output buffers CL = Average output loading capacitance, typically 10 pF = Average C-cell switching frequency, typically fmc F/10 fms = Average R-cell switching frequency, typically F/10 fn = Average input buffer switching frequency, typically F/5 fp = Average output buffer switching frequency, typically F/5 fq1 = Frequency of routed clock A fq2 = Frequency of routed clock B fs1 = Frequency of dedicated array clock The eX, SX-A and RTSX-S Power Calculator can be used to estimate the total power dissipation (static and dynamic) of eX devices and can be found at http://www.actel.com/products/rescenter/power/ calculators.asp.
Ceqsm =
Thermal Characteristics
The temperature variable in the Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. EQ 1-1, shown below, can be used to calculate junction temperature.
EQ 1-1 Junction Temperature = T + Ta(1)
Where:
Ta = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient = ja * P P = Power ja = Junction to ambient of package. ja numbers are
located in the "Package Thermal Characteristics" section below.
Package Thermal Characteristics
The device junction-to-case thermal characteristic is jc, and the junction-to-ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. jc is provided for reference. The maximum junction temperature is 150C. The maximum power dissipation allowed for eX devices is a function of ja. A sample calculation of the absolute maximum power dissipation allowed for a TQFP 100-pin package at commercial temperature and still air is as follows:
Max. junction temp. (C) - Max. ambient temp. (C) 150C - 70C Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = ---------------------------------- = 2.39W ja (C/W) 33.5C/W ja Package Type Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP) Chip Scale Package (CSP) Chip Scale Package (CSP) Chip Scale Package (CSP) Pin Count 64 100 49 128 180 jc 12.0 14.0 Still Air 42.4 33.5 72.2 54.1 57.8 1.0 m/s 200 ft/min 36.3 27.4 59.5 44.6 47.6 2.5 m/s 500 ft/min 34.0 25.0 54.1 40.6 43.3 Units C/W C/W C/W C/W C/W
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eX Family FPGAs
eX Timing Model
Input Delays Internal Delays Combinatorial Cell Predicted Routing Delays Output Delays
I/O Module t INYH = 0.7 ns
t IRD1 = 0.3 ns t IRD2 = 0.4 ns
I/O Module
t PD = 0.7 ns
t RD1 = 0.3 ns t RD4 = 0.7 ns t RD8 = 1.2 ns I/O Module
t DHL = 2.6 ns
Register Cell t ENZL= 1.9 ns t SUD = 0.5 ns t HD = 0.0 ns Routed Clock D Q t RD1 = 0.3 ns t DHL = 2.6 ns
t RCKH = 1.3 ns (100% Load)
t RCO= 0.6 ns Register Cell t IRD1 = 0.3 ns t SUD = 0.5 ns t HD = 0.0 ns D Q t RD1 = 0.3 ns
I/O Module
I/O Module t INYH = 1.3 ns
t ENZL= 1.9 ns
t DHL = 2.6 ns
Hard-Wired Clock
t HCKH = 1.1 ns
t RCO= 0.6 ns
Note: Values shown for eX128-P, worst-case commercial conditions (5.0V, 35pF Pad Load). Figure 1-14 * eX Timing Model
Hardwired Clock
External Setup = = = = tINYH + tIRD1 + tSUD - tHCKH 0.7 + 0.3 + 0.5 - 1.1 = 0.4 ns tHCKH + tRCO + tRD1 + tDHL 1.1 + 0.6 + 0.3 + 2.6 = 4.6 ns
Routed Clock
External Setup = = = = tINYH + tIRD2 + tSUD - tRCKH 0.7 + 0.4 + 0.5 - 1.3= 0.3 ns tRCKH + tRCO + tRD1 + tDHL 1.3+ 0.6 + 0.3 + 2.6 = 4.8 ns
Clock-to-Out (Pad-to-Pad), typical
Clock-to-Out (Pad-to-Pad), typical
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Output Buffer Delays
E D
TRIBUFF
PAD T AC test loads (shown below) o
In Out VOL
VCC 50% 50% VOH 1.5 V tDLH
GND 1.5 V tDHL
En Out
VCC 50% 50% GND VCC 1.5 V 10% VOL tENZL tENLZ
En
Out GND t ENZH
VCC 50% 50% VOH 1.5 V tENHZ
GND 90%
Table 1-13 * Output Buffer Delays
AC Test Loads
Load 1 (used to measure propagation delay) To the output under test 35 pF Load 2 (Used to measure enable delays) VCC GND R to VCC for tPZL R to GND for tPHZ R = 1 k 35 pF Load 3 (Used to measure disable delays) VCC GND R to VCC for tPLZ R to GND for tPHZ R = 1 k 5 pF
To the output under test
To the output under test
Figure 1-15 * AC Test Loads
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eX Family FPGAs
Input Buffer Delays
C-Cell Delays
S A B VCC 50% 50% VCC 50% tPD
50%
PAD
INBUF
Y
Y
S, A or B
3V In Out GND 1.5 V 1.5 V VCC 50% tINY tINY 0V
GND 50% tPD VCC GND tPD 50%
Out GND Out
50% tPD
Table 1-15 * C-Cell Delays
Table 1-14 * Input Buffer Delays
Cell Timing Characteristics
D CLK PRESET CLR Q
D t SUD CLK
(Positive edge triggered) tHD t HPWH , t RPWH tRCO tH P tHPWL, tRPWL tCLR t PRESET
Q CLR t WASYN PRESET
Figure 1-16 * Flip-Flops
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Timing Characteristics
Timing characteristics for eX devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all eX family members. Internal routing delays are device-dependent. Design dependency means actual delays are not determined until after placement and routing of the user's design are complete. Delay values may then be determined by using the Timer utility or performing simulation with postlayout delays.
Long Tracks
Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three to five antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, no more than six percent of nets in a fully utilized device require long tracks. Long tracks contribute approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout routing delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to six percent of the nets in a design may be designated as critical.
Timing Derating
eX devices are manufactured with a CMOS process. Therefore, device performance varies according to temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing.
Temperature and Voltage Derating Factors
Table 1-16 * Temperature and Voltage Derating Factors (Normalized to Worst-Case Commercial, TJ = 70C, VCCA = 2.3V) Junction Temperature (TJ) VCCA 2.3 2.5 2.7 -55 0.79 0.74 0.69 -40 0.80 0.74 0.70 0 0.87 0.81 0.76 25 0.88 0.83 0.78 70 1.00 0.93 0.88 85 1.04 0.97 0.91 125 1.13 1.06 1.00
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eX Family FPGAs
eX Family Timing Characteristics
Table 1-17 * eX Family Timing Characteristics (Worst-Case Commercial Conditions, VCCA = 2.3 V, TJ = 70C) `-P' Speed Parameter tPD tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN tRECASYN tHASYN tINYH tINYL tINYH tINYL tINYH tINYL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Hold Time Input Data Pad-to-Y HIGH Input Data Pad-to-Y LOW Input Data Pad-to-Y HIGH Input Data Pad-to-Y LOW Input Data Pad-to-Y HIGH Input Data Pad-to-Y LOW Delays2 0.3 0.4 0.5 0.7 1.2 1.7 0.4 0.6 0.8 1.0 1.7 2.5 0.5 0.8 1.1 1.3 2.4 3.5 ns ns ns ns ns ns FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay 0.5 0.0 1.3 0.3 0.3 0.6 0.8 0.7 0.9 0.7 0.9 0.6 0.6 0.7 0.7 0.0 1.9 0.5 0.5 0.9 1.1 1.0 1.3 1.0 1.3 0.9 0.8 0.9 1.0 0.0 2.6 0.7 0.7 1.3 1.5 1.4 1.8 1.4 1.8 1.3 1.2 1.3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description
1
`Std' Speed Min. Max. 1.0 0.1 0.5 0.5 0.6 0.8 1.0 1.7 2.5
`-F' Speed Min. Max. 1.4 0.2 0.7 0.7 0.8 1.1 1.3 2.4 3.5 Units ns ns ns ns ns ns ns ns ns
Min.
Max. 0.7 0.1 0.3 0.3 0.4 0.5 0.7 1.2 1.7
C-Cell Propagation Delays Predicted Routing Delays
Internal Array Module
2
FO=1 Routing Delay, DirectConnect FO=1 Routing Delay, FastConnect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay
2.5 V Input Module Propagation Delays
3.3 V Input Module Propagation Delays
5.0 V Input Module Propagation Delays
Input Module Predicted Routing
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Table 1-18 * eX Family Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.3 V, VCCI = 4.75 V, TJ = 70C) `-P' Speed Parameter Description Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Dedicated (Hard-Wired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency 2.8 357 1.4 1.4 <0.1 4.0 250 1.1 1.1 2.0 2.0 <0.1 5.6 178 1.6 1.6 2.8 2.8 <0.1 2.3 2.3 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW* tRCKSW* tRCKSW* Input LOW to HIGH (Light Load) (Pad to R-Cell Input) MAX. Input HIGH to LOW (Light Load) (Pad to R-Cell Input) MAX. Input LOW to HIGH (50% Load) (Pad to R-Cell Input) MAX. Input HIGH to LOW (50% Load) (Pad to R-Cell Input) MAX. Input LOW to HIGH (100% Load) (Pad to R-Cell Input) MAX. Input HIGH to LOW (100% Load) (Pad to R-Cell Input) MAX. Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.5 1.5 0.2 0.1 0.1 1.1 1.0 1.2 1.2 1.3 1.3 2.1 2.1 0.3 0.2 0.1 1.6 1.4 1.7 1.7 1.9 1.9 3.0 3.0 0.4 0.3 0.2 2.2 2.0 2.4 2.4 2.6 2.6 ns ns ns ns ns ns ns ns ns ns ns
Note: *Clock skew improves as the clock network becomes more heavily loaded.
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eX Family FPGAs
Table 1-19 * eX Family Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.3V, VCCI = 2.3 V or 3.0V, TJ = 70C) `-P' Speed Parameter Description Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Dedicated (Hard-Wired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency 2.8 357 1.4 1.4 <0.1 4.0 250 1.1 1.1 2.0 2.0 <0.1 5.6 178 1.6 1.6 2.8 2.8 <0.1 2.3 2.3 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW* tRCKSW* tRCKSW* Input LOW to HIGH (Light Load) (Pad to R-Cell Input) MAX. Input HIGH to LOW (Light Load) (Pad to R-Cell Input) MAX. Input LOW to HIGH (50% Load) (Pad to R-Cell Input) MAX. Input HIGH to LOW (50% Load) (Pad to R-Cell Input) MAX. Input LOW to HIGH (100% Load) (Pad to R-Cell Input) MAX. Input HIGH to LOW (100% Load) (Pad to R-Cell Input) MAX. Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 1.4 1.4 0.2 0.2 0.1 1.0 1.0 1.2 1.2 1.4 1.4 2.0 2.0 0.3 0.2 0.1 1.4 1.4 1.7 1.7 2.0 2.0 2.8 2.8 0.4 0.3 0.2 2.0 2.0 2.4 2.4 2.8 2.8 ns ns ns ns ns ns ns ns ns ns ns
Note: *Clock skew improves as the clock network becomes more heavily loaded.
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v4.3
eX Family FPGAs
Table 1-20 * eX Family Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.3 V, TJ = 70C) `-P' Speed Parameter Description Timing1 (VCCI = 2.3 V) 3.3 3.5 11.6 2.5 11.8 3.4 2.1 2.4 0.034 0.016 0.05 4.7 5.0 16.6 3.6 16.9 4.9 3.0 5.67 0.046 0.022 0.072 6.6 7.0 23.2 5.1 23.7 6.9 4.2 7.94 0.066 0.05 0.1 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
2.5 V LVCMOS Output Module tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH dTHL dTHLS
Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Data-to-Pad HIGH to LOW--Low Slew Enable-to-Pad, Z to L Enable-to-Pad Z to L--Low Slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Delay vs. Load LOW to HIGH Delta Delay vs. Load HIGH to LOW Delta Delay vs. Load HIGH to LOW--Low Slew
1
3.3 V LVTTL Output Module Timing (VCCI = 3.0 V) tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH dTHL dTHLS Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Data-to-Pad HIGH to LOW--Low Slew Enable-to-Pad, Z to L Enable-to-Pad Z to L--Low Slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Delay vs. Load LOW to HIGH Delta Delay vs. Load HIGH to LOW Delta Delay vs. Load HIGH to LOW--Low Slew
*
2.8 2.7 9.7 2.2 9.7 2.8 2.8 2.6 0.02 0.016 0.05
4.0 3.9 13.9 3.2 13.9 4.0 4.0 3.8 0.03 0.022 0.072
5.6 5.4 19.5 4.4 19.6 5.6 5.6 5.3 0.046 0.05 0.1
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF
5.0 V TTL Output Module Timing (VCCI = 4.75 V) tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Data-to-Pad HIGH to LOW--Low Slew Enable-to-Pad, Z to L Enable-to-Pad Z to L--Low Slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z 2.0 2.6 6.8 1.9 6.8 2.1 3.3 2.9 3.7 9.7 2.7 9.8 3.0 4.8 4.0 5.2 13.6 3.8 13.7 4.1 6.6 ns ns ns ns ns ns ns
Note: *Delays based on 35 pF loading.
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eX Family FPGAs
Pin Description
CLKA/B Routed Clock A and B TCK, I/O Test Clock
These pins are clock inputs for clock distribution networks. Input levels are compatible with standard TTL or LVTTL specifications. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating.
GND Ground
Test clock input for diagnostic probe and device programming. In flexible mode, TCK becomes active when the TMS pin is set LOW (refer to Table 1-4 on page 1-9). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state.
TDI, I/O Test Data Input
LOW supply voltage.
HCLK Dedicated (Hardwired) Array Clock
This pin is the clock input for sequential modules. Input levels are compatible with standard TTL or LVTTL specifications. This input is directly wired to each R-cell and offers clock speeds independent of the number of Rcells being driven. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating.
I/O Input/Output
Serial input for boundary scan testing and diagnostic probe. In flexible mode, TDI is active when the TMS pin is set LOW (refer to Table 1-4 on page 1-9). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state.
TDO, I/O Test Data Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Based on certain configurations, input and output levels are compatible with standard TTL or LVTTL specifications. Unused I/O pins are automatically tristated by the Designer software.
LP Low Power Pin
Serial output for boundary scan testing. In flexible mode, TDO is active when the TMS pin is set LOW (refer to Table 1-4 on page 1-9). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. When Silicon Explorer is being used, TDO will act as an output when the "checksum" command is run. It will return to user I/O when "checksum" is complete.
TMS Test Mode Select
Controls the low power mode of the eX devices. The device is placed in the low power mode by connecting the LP pin to logic HIGH. In low power mode, all I/Os are tristated, all input buffers are turned OFF, and the core of the device is turned OFF. To exit the low power mode, the LP pin must be set LOW. The device enters the low power mode 800 ns after the LP pin is driven to a logic HIGH. It will resume normal operation 200 s after the LP pin is driven to a logic LOW. LP pin should not be left floating. Under normal operating condition it should be tied to GND via 10 k resistor.
NC No Connection
The TMS pin controls the use of the IEEE 1149.1 Boundary scan pins (TCK, TDI, TDO, TRST). In flexible mode when the TMS pin is set LOW, the TCK, TDI, and TDO pins are boundary scan pins (refer to Table 1-4 on page 1-9). Once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the "logic reset" state. At this point, the boundary scan pins will be released and will function as regular I/O pins. The "logic reset" state is reached five TCK cycles after the TMS pin is set HIGH. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications.
TRST, I/O Boundary Scan Reset Pin
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device.
PRA/PRB, I/O Probe A/B
The Probe pin is used to output data from any userdefined design node within the device. This diagnostic pin can be used independently or in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device. The Probe pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality.
Once it is configured as the JTAG Reset pin, the TRST pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. The TRST pin is equipped with an internal pull-up resistor. This pin functions as an I/O when the "Reserve JTAG Reset Pin" is not selected in the Designer software.
VCCI Supply Voltage
Supply voltage for I/Os.
VCCA Supply Voltage
Supply voltage for Array.
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eX Family FPGAs
Package Pin Assignments
64-Pin TQFP
64 1
64-Pin TQFP
Figure 2-1 * 64-Pin TQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v4.3
2-1
eX Family FPGAs
64-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 eX64 Function GND TDI, I/O I/O TMS GND VCCI I/O I/O NC NC TRST, I/O I/O NC GND I/O I/O I/O I/O VCCI I/O PRB, I/O VCCA GND I/O HCLK I/O I/O I/O I/O I/O I/O TDO, I/O eX128 Function GND TDI, I/O I/O TMS GND VCCI I/O I/O I/O I/O TRST, I/O I/O I/O GND I/O I/O I/O I/O VCCI I/O PRB, I/O VCCA GND I/O HCLK I/O I/O I/O I/O I/O I/O TDO, I/O Pin Number 33 34 35 36 37 38 39 40 41 42 43 44 45* 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
64-Pin TQFP eX64 Function GND I/O I/O VCCA VCCI I/O I/O NC NC I/O I/O VCCA GND/LP GND I/O I/O I/O I/O I/O VCCI I/O I/O CLKA CLKB VCCA GND PRA, I/O I/O VCCI I/O I/O TCK, I/O eX128 Function GND I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O VCCA GND/ LP GND I/O I/O I/O I/O I/O VCCI I/O I/O CLKA CLKB VCCA GND PRA, I/O I/O VCCI I/O I/O TCK, I/O
Note: *Please read the LP pin descriptions for restrictions on their use.
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v4.3
eX Family FPGAs
100-Pin TQFP
100 1
100-Pin TQFP
Figure 2-2 * 100-Pin TQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v4.3
2-3
eX Family FPGAs
100-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 eX64 Function GND TDI, I/O NC NC NC I/O TMS VCCI GND NC NC I/O NC I/O NC TRST, I/O NC I/O NC VCCI I/O NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA eX128 Function GND TDI, I/O NC NC NC I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCI I/O I/O NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA eX256 Function GND TDI, I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
100-Pin TQFP eX64 Function GND NC I/O HCLK I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O NC GND NC NC NC I/O I/O VCCA VCCI NC I/O NC I/O NC I/O NC I/O VCCA GND/LP GND I/O eX128 Function GND NC I/O HCLK I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND NC NC NC I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND/LP GND I/O eX256 Function GND NC I/O HCLK I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND/LP GND I/O
Note: *Please read the LP pin descriptions for restrictions on their use.
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v4.3
eX Family FPGAs
100-Pin TQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 eX64 Function I/O NC NC NC NC NC I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O CLKA CLKB NC VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O eX128 Function I/O I/O NC NC NC I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O CLKA CLKB NC VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O eX256 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O CLKA CLKB NC VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O
Note: *Please read the LP pin descriptions for restrictions on their use.
v4.3
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eX Family FPGAs
49-Pin CSP
A1 Ball Pad Corner 1 A B C D E F G
Figure 2-3 * 49-Pin CSP (Top View)
2
3
4
5
6
7
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
2 -6
v4.3
eX Family FPGAs
49-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7* C1 C2 C3 C4 C5 C6 C7 D1 D2 D3 D4 eX64 Function I/O I/O I/O I/O VCCA I/O I/O TCK, I/O I/O I/O PRA, I/O CLKA I/O GND/LP* I/O TDI, I/O VCCI GND CLKB VCCA I/O I/O TMS GND GND eX128 Function I/O I/O I/O I/O VCCA I/O I/O TCK, I/O I/O I/O PRA, I/O CLKA I/O GND/LP* I/O TDI, I/O VCCI GND CLKB VCCA I/O I/O TMS GND GND Pin Number D5 D6 D7 E1 E2 E3 E4 E5 E6 E7 F1 F2 F3 F4 F5 F6 F7 G1 G2 G3 G4 G5 G6 G7
49-Pin CSP eX64 Function VCCA I/O I/O I/O TRST, I/O VCCI GND I/O I/O VCCI I/O I/O I/O I/O HCLK I/O TDO, I/O I/O I/O I/O PRB, I/O VCCA I/O I/O eX128 Function VCCA I/O I/O I/O TRST, I/O VCCI GND I/O I/O VCCI I/O I/O I/O I/O HCLK I/O TDO, I/O I/O I/O I/O PRB, I/O VCCA I/O I/O
Note: *Please read the LP pin descriptions for restrictions on their use.
v4.3
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eX Family FPGAs
128-Pin CSP
A1 Ball Pad Corner 1 A B C D E F G H J K L M 2 3 4 5 6 7 8 9 10 11 12
Figure 2-4 * 128-Pin CSP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
2 -8
v4.3
eX Family FPGAs
128-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 eX64 Function I/O TCK, I/O VCCI I/O I/O VCCA I/O I/O VCCI I/O I/O I/O TMS I/O I/O I/O I/O PRA, I/O CLKB I/O I/O I/O GND I/O I/O TDI, I/O I/O I/O I/O CLKA I/O I/O I/O NC NC eX128 Function I/O TCK, I/O VCCI I/O I/O VCCA I/O I/O VCCI I/O I/O I/O TMS I/O I/O I/O I/O PRA, I/O CLKB I/O I/O I/O GND I/O I/O TDI, I/O I/O I/O I/O CLKA I/O I/O I/O I/O I/O eX256 Function I/O TCK, I/O VCCI I/O I/O VCCA I/O I/O VCCI I/O I/O I/O TMS I/O I/O I/O I/O PRA, I/O CLKB I/O I/O I/O GND I/O I/O TDI, I/O I/O I/O I/O CLKA I/O I/O I/O I/O I/O Pin Number C12 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E9 E10 E11* E12 F1 F2 F3 F4 F9 F10 F11 F12 G1 G2 G3 G4 G9 G10
128-Pin CSP eX64 Function I/O NC I/O I/O I/O I/O GND I/O GND I/O I/O I/O VCCI NC VCCI I/O GND GND I/O GND/LP* VCCA NC NC NC I/O GND NC I/O I/O NC TRST, I/O I/O GND GND NC eX128 Function I/O I/O I/O I/O I/O I/O GND I/O GND I/O I/O I/O VCCI I/O VCCI I/O GND GND I/O GND/LP* VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O TRST, I/O I/O GND GND I/O eX256 Function I/O I/O I/O I/O I/O I/O GND I/O GND I/O I/O I/O VCCI I/O VCCI I/O GND GND I/O GND/LP* VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O TRST, I/O I/O GND GND I/O
Note: *Please read the LP pin descriptions for restrictions on their use.
v4.3
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eX Family FPGAs
128-Pin CSP Pin Number G11 G12 H1 H2 H3 H4 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 K1 K2 K3 K4 K5 K6 K7 eX64 Function I/O NC GND I/O VCCI GND I/O VCCI VCCA NC NC I/O VCCI I/O I/O I/O GND I/O GND I/O I/O NC NC I/O I/O I/O I/O PRB, I/O HCLK eX128 Function I/O I/O GND I/O VCCI GND I/O VCCI VCCA I/O NC I/O VCCI I/O I/O I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O HCLK eX256 Function I/O I/O GND I/O VCCI GND I/O VCCI VCCA I/O VCCA I/O VCCI I/O I/O I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O HCLK Pin Number K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12
128-Pin CSP eX64 Function I/O I/O I/O TDO, I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O NC VCCI GND I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O eX128 Function I/O I/O I/O TDO, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O eX256 Function I/O I/O I/O TDO, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O
Note: *Please read the LP pin descriptions for restrictions on their use.
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v4.3
eX Family FPGAs
180-Pin CSP
A1 Ball Pad Corner 1 A B C D E F G H J K L M N P
Figure 2-5 * 180-Pin CSP
2
3
4
5
6
7
8
9 10 11 12 13 14
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v4.3
2-11
eX Family FPGAs
180-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 eX256 Function I/O I/O GND NC NC NC NC NC NC NC NC I/O I/O I/O I/O I/O TCK, I/O VCCI I/O I/O VCCA I/O I/O VCCI I/O I/O I/O I/O I/O TMS I/O I/O I/O I/O PRA, I/O
180-Pin CSP Pin Number C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 eX256 Function CLKB I/O I/O I/O GND I/O I/O I/O I/O TDI, I/O I/O I/O I/O CLKA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GND I/O I/O I/O VCCI I/O
180-Pin CSP Pin Number F1 F2 F3 F4 F5 F10 F11 F12* F13 F14 G1 G2 G3 G4 G5 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 eX256 Function I/O I/O VCCI I/O GND GND I/O GND/LP* VCCA I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O VCCA I/O I/O TRST, I/O I/O GND GND I/O I/O I/O I/O I/O GND I/O VCCI GND
180-Pin CSP Pin Number J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 eX256 Function I/O VCCI VCCA I/O I/O I/O VCCA I/O VCCI I/O I/O I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O HCLK I/O I/O I/O TDO, I/O I/O I/O I/O I/O
Note: *Please read the LP pin descriptions for restrictions on their use.
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v4.3
eX Family FPGAs
180-Pin CSP Pin Number M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 eX256 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O GND I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC NC NC NC
180-Pin CSP Pin Number P10 P11 P12 P13 eX256 Function NC NC GND I/O
Note: *Please read the LP pin descriptions for restrictions on their use.
v4.3
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eX Family FPGAs
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version v4.2 (June 2004) Changes in current version (v4.3) Page The "Ordering Information" was updated with RoHS information. The TQFP measurement ii was also updated. The "Dedicated Test Mode" was updated. 1-9 Note 5 was added to the "3.3V LVTTL Electrical Specifications" and "5.0V TTL Electrical 1-15 Specifications" tables The "LP Low Power Pin" description was updated. v4.1 v4.0 v3.0 The "eX Timing Model" was updated. The "Development Tool Support" section was updated. The "Package Thermal Characteristics" section was updated. The "Product Profile" section was updated. The "Ordering Information" section was updated. The "Temperature Grade Offerings" section is new. The "Speed Grade and Temperature Grade Matrix" section is new. The "General Description" section was updated. The "Clock Resources" section was updated. Table 1-1 * Connections of Routed Clock Networks, CLKA and CLKB is new. The "User Security" section was updated. The "I/O Modules" section was updated. The "Hot Swapping" section was updated. The "Power Requirements" section was updated. The "Low Power Mode" section was updated. The "Boundary Scan Testing (BST)" section was updated. The "Dedicated Test Mode" section was updated. The "Flexible Mode" section was updated. Table 1-5 * Boundary-Scan Pin Configurations and Functions is new. The "TRST Pin" section was updated. The "Probing Capabilities" section is new. The "Programming" section was updated. The "Probing Capabilities" section was updated. The "Silicon Explorer II Probe" section was updated. The "Design Considerations" section was updated. The "Development Tool Support" section was updated. The "Absolute Maximum Ratings*" section was updated. The "Temperature and Voltage Derating Factors" section was updated. The "TDI, I/O Test Data Input" section was updated. 1-26 1-18 1-12 1-17 1-i 1-ii 1-ii 1-ii 1-1 1-4 1-4 1-5 1-5 1-6 1-6 1-6 1-9 1-9 1-9 1-9 1-9 1-10 1-10 1-10 1-10 1-11 1-12 1-13 1-21 1-26
v4.3
3-1
eX Family FPGAs
Previous version v3.0 (continued)
Changes in current version (v4.3) The "TDO, I/O Test Data Output" section was updated. The "TMS Test Mode Select" section was updated. The "TRST, I/O Boundary Scan Reset Pin" section was updated. All VSV pins were changed to VCCA. The change affected the following pins: 64-Pin TQFP -Pin 36 100-Pin TQFP -Pin 57 49-Pin CSP -Pin D5 128-Pin CSP-Pin H11 and Pin J1 for eX256 180-Pin CSP -Pins J12 and K2
Page 1-26 1-26 1-26
v2.0.1
The "Recommended Operating Conditions" section has been changed. The "3.3V LVTTL Electrical Specifications" section has been updated. The "5.0V TTL Electrical Specifications" section has been updated. The "Total Dynamic Power (mW)" section is new. The "System Power at 5%, 10%, and 15% Duty Cycle" section is new. The "eX Timing Model" section has been updated.
1-13 1-15 1-15 1-8 1-8 1-18 1-5
Advanced v0.4
The I/O Features table, Table 1-2 on page 1-5, was updated.
The table, "Standby Power of eX Devices in LP Mode Typical Conditions, VCCA, VCCI = 1-6 2.5V, TJ = 25x C" section, was updated. "Typical eX Standby Current at 25C" section is a new table. 1-13 The table in the section, "Package Thermal Characteristics" section has been updated for 1-17 the 49-Pin CSP. The "eX Timing Model" section has been updated. 1-18 The timing numbers found in, "eX Family Timing Characteristics" section have been 1-22 updated. The VSV pin has been added to the "Pin Description" section. 1-26 Please see the following pin tables for the VSV pin and an important footnote including the 2-1, 2-3, 2-6, 2-11 pin: "64-Pin TQFP","100-Pin TQFP",, ,"128-Pin CSP", and "180-Pin CSP". The figure, "64-Pin TQFP" section has been updated. Advanced v0.3 In the Product Profile, the Maximum User I/Os for eX64 was changed to 84. In the Product Profile table, the Maximum User I/Os for eX128 was changed to 100. 2-1 1-i 1-i
3 -2
v4.3
eX Family FPGAs
Previous version Advanced v0.2
Changes in current version (v4.3) The Mechanical Drawings section has been removed from the data sheet. The mechanical drawings are now contained in a separate document, "Package Characteristics and Mechanical Drawings," available on the Actel web site. A new section describing "Clock Resources"has been added. A new table describing "I/O Features"has been added. The "Pin Description"section has been updated and clarified.
Page
1-4 1-5 1-26
The original Electrical Specifications table was separated into two tables (2.5V and 3.3/ Page 8 and 9 5.0V). In both tables, several different currents are specified for VOH and VOL. A new table listing 2.5V low power specifications and associated power graphs were added. page 9 Pin functions for eX256 TQ100 have been added to the "100-Pin TQFP"table. 2-3 A CS49 pin drawing and pin assignment table including eX64 and eX128 pin functions have page 26 been added. A CS128 pin drawing and pin assignment table including eX64, eX128, and eX256 pin pages 26-27 functions have been added. A CS180 pin drawing and pin assignment table for eX256 pin functions have been added. pages 27, 31 Advanced v.1 The following table note was added to the eX Timing Characteristics table for clarification: pages 14-15 Clock skew improves as the clock network becomes more heavily loaded.
v4.3
3-3
eX Family FPGAs
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families.
Export Administration Regulations (EAR)
The product described in this datasheet is subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.
3 -4
v4.3
Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners.
http://www.actel.com
Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Actel Europe Ltd. Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 (0) 1276 401 450 Fax +44 (0) 1276 401 490 Actel Japan www.jp.actel.com EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 Actel Hong Kong www.actel.com.cn Suite 2114, Two Pacific Place 88 Queensway, Admiralty Hong Kong Phone +852 2185 6460 Fax +852 2185 6488
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